In data communication applications, it is frequently necessary to transmit data to inductive loads. For example, data transceivers used in local area networks (LANs) include data driver circuits having outputs which are connected to an isolation transformer. Such isolation transformers present an inductive load which causes the output of the driver to either undershoot or overshoot. Standards have been developed, such as in Ethernet applications, which specify the maximum amount of permissible overshoot and undershoot.
Attempts have been made to develop data driver circuits which comply with the undershoot/overshoot specifications, but which are also capable of rapidly discharging the inductive load. Referring to the drawings, FIG. 1 shows a conventional driver circuit of the type used in Ethernet LAN applications.
The conventional driver circuit 10 includes an output drive stage 18 having a pair of data inputs on lines 24 and 28 which receive data input signals RXOP and RXON, respectively. The driver stage includes a differential amplifier input comprised of transistors Q.sub.5 and Q.sub.6 having resistive loads R.sub.3 and R.sub.4. The output of the differential amplifier drives a pair of emitter-follower configured transistors Q.sub.9 and Q.sub.10.
The differential output of the drive stage is at the emitters of transistors Q.sub.9 and Q.sub.10 which are connected to lines 32 and 34, respectively. The output lines are coupled to the primary winding of an isolation transformer (not depicted) having a resistor connected in parallel. The transformer and parallel resistor equivalent circuit 20 is represented by inductor L and resistor R.sub.L. The differential output signals are RXP and RXN.
When a data packet is transmitted to the transceiver, driver circuit 10 in the transceiver receives the data packet on inputs 24 and 28 as signals RXOP and RXON. The data packet is retransmitted by the driver circuit and appears at lines 32 and 34 as output signals RXP and RXN.
For LAN protocols such as Ethernet, an idle period is required between transmission of data packets. During the idle period, inputs RXON and RXOP, and thus outputs RXP and RXN, are initially held at their respective maximum values. Outputs RXP and RXN must be maintained at these values for a predetermined time period referred to as the high time t.sub.high. Period t.sub.high must be at least 200 nanoseconds and no longer than 8 microseconds. Ideally, the inductive load is discharged by the end of the idle period.
The driver circuit is forced to the idle mode by an enable signal coupled to line 26. The enable signal is generated by a receive squelch circuit (not depicted) which senses the presence of a data packet. The enable signal is caused to go high (a logic "1") when a data packet is being received and is caused to go low (a logic ".0.") when a data packet terminates. The idle period commences when the enable signal goes low.
The conventional driver circuit includes a switch circuit 12 which receives the enable signal on line 26 and an associated time delay circuit 14 which determines the duration of the high time t.sub.high. Switch circuit 12 includes a differential comparator circuit made up of transistors Q.sub.2 and Q.sub.3, with transistor Q.sub.2 biased by a pair of resistors R.sub.6 and R.sub.5 connected between the supply voltage and ground. The enable signal is coupled to the base of transistor Q.sub.3 such that Q.sub.3 is conductive when the enable signal is high (a data packet is being received) and non-conductive when the enable signal is low.
Time delay circuit 14 includes a resistor R.sub.1 and capacitor C connected in parallel between the positive supply voltage and the collector of transistor Q.sub.3. The RC time constant of R.sub.1 and C will provide a time delay as will be described.
The collector of transistor Q.sub.3 is also coupled to the base of a transistor Q.sub.4 which, in turn, drives the bases of a pair of transistors Q.sub.7 and Q.sub.8. The collectors of transistors Q.sub.7 and Q.sub.8 are connected to the collectors of transistors Q.sub.5 and Q.sub.6, respectively, and the emitters of the four transistors are connected in common.
The operation of the conventional drive circuit will be described in connection with FIG. 1 and the timing diagram of FIG. 2. The top waveform represents the enable signal and the next waveform represents a mode control signal present at node 33 of FIG. 1. The lower waveforms represent the differential data outputs RXP and RXN driving the inductive load.
When a data packet is being received, the enable signal is caused to go high as shown at point A. The high enable signal will turn on transistor Q.sub.3 and cause the collector of Q.sub.3 to drop, thereby charging capacitor C of the time delay circuit. The low Q.sub.3 collector voltage will also turn off transistors Q.sub.4, Q.sub.7 and Q.sub.8.
When transistors Q.sub.7 and Q.sub.8 are off, the output driver stage 18 is free to retransmit the received data packet to lines 32 and 34 as can be seen by waveforms RXP and RXN of FIG. 1. The typical data modulation scheme prescribes that a data transition, occur at every bit, therefore the output signal has substantially no D.C. component which would tend to charge the inductive load. At the end of the data packet, the receive squelch detects the absence of data and causes the enable signal to go low at point B. As a result, Q.sub.3 is turned off. This is the beginning of the high time period t.sub.high.
Capacitor C will then proceed to discharge through resistor R1. The collector of transistor Q.sub.3 will slowly rise, thereby causing the emitter of transistor Q.sub.4 to rise. This will cause the mode control signal at node 33 to increase as can be seen by the FIG. 2 waveform.
At the same time the enable signal goes low, the source (not depicted) of input data RXOP and RXON on lines 24 and 28 will force the input data to remain at their respective maximum values. This will cause the output data signals RXP and RXN to remain at their respective maximum values as shown in FIG. 2. During this specified high period t.sub.high, the data output signals have a substantial D.C. component which charges the inductive load L.
Eventually, the mode control voltage at node 33 will have increased sufficiently to turn on transistors Q.sub.7 and Q.sub.8. Transistors Q.sub.7 and Q.sub.8 will then draw current from load resistors R3 and R.sub.4 thereby reducing the differential output signals RXP and RXN as shown at point C. This is the end of the high time period t.sub.high.
It is desireable that the outputs RXP and RXN both approach the midlevel value and remain there throughout the idle period while the inductor L discharges. However, because of the presence of the load inductor L, there will be a tendency for the positive signal RXP to undershoot and the negative signal RXN to overshoot as shown in FIG. 2 at point D by a very substantial amount. The amount of undershoot/overshoot can be reduced by reducing the high time period t.sub.high, but the period must be at least as long as the specified minimum period.
One conventional approach to reducing undershoot/overshoot is to employ a continuously active feedback circuit which monitors the data output signals and limits the amount of overshoot/undershoot. However, once the inductive load becomes substantially discharged, the load appears as a D.C. short circuit. The continuously active feedback circuit will attempt to force the output voltage to some minimum value which is determined by various factors including the inherent offset voltages which are present in any feedback system. This minimum value will invariably differ from the actual voltage across the discharged inductor. The feedback network will attempt to force the inductor voltage to the offset voltage thereby introducing large currents into the inductor. These currents will leave the isolation transformer inductance partially charged, thereby adversely affecting the operation of the transformer when the next data packet is received.
The present invention overcomes the above-noted shortcomings of prior art drive circuits. The magnitude of the overshoot/undershoot can be positively maintained within stringent specifications, yet the inductive load will be allowed to quickly discharge before receipt of the next data packet. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.